Typically, the thickness of a silicon wafer that is used in the fabrication of integrated circuit chips is approximately 500 microns. Usually, only the first micron at the top of the silicon wafer is used for transistor operation. Silicon-on-insulator (SOI) technologies provide convenient methods to produce devices in the top surface of the silicon wafer. Briefly, SOI can be described as completely surrounding devices with an insulator, rather than with a pn junction.
SOI carries the possibility of reducing process complexity for the fabrication of semiconductor devices. Moreover, SOI provides radiation immunity, which can be important for space and military applications. Junction isolation is less effective in high-radiation environments, since transient photocurrents are produced by gamma rays in pn junctions. Another advantage of SOI is that reduced capacitance of semiconductor devices that are produced by SOI increases the operational speed of transistors designed with the same dimensions as previous generations. That is, reductions in parasitic capacitance increase circuit speed. Circuit speed is further enhanced by reductions in microchip size allowed by SOI technologies.
An SOI structure can be formed using wafer bonding. This technology fuses two oxidized silicon wafers together using a high-temperature furnace. While this technology has produced favorable results in many applications, the approach is costly and is limited by the ability of the approach to achieve dimensional uniformity.
Another SOI technology is referred to as Separation by IMplanted OXygen (SIMOX). This technology has emerged as a promising candidate for Ultra Large Scale Integration (ULSI) CMOS applications. SIMOX wafers have been used in the fabrication of semiconductor devices that offer significant advantages in gain, speed, maximum operating temperature, and power consumption. Conventionally, SIMOX wafers have been fabricated by high dose, e.g. 1.8.times.10.sup.18 ions/cm.sup.2 and high energy, e.g., 150-200 KeV, ion beam implantation of O.sup.+ ions. However, a recent development in SIMOX technology, referred to as Low Energy SIMOX (LES), uses low dose implantations of 1-6.times.10.sup.17 ions/cm.sup.2 at low energy in the range of 20-80 KeV with favorable results. It has been demonstrated that LES can produce SIMOX wafers having a 12.5 nm silicon overlayer and a 36 nm buried silicon dioxide layer by means of an ion beam implantation of O.sup.+ at 20 KeV, with a total dose of 15.times.10.sup.17 ions/cm.sup.2, followed by a high temperature anneal. LES structures offer lower defect densities and lower production costs relative to conventional SIMOX techniques.
The operation of an ion beam implantation device is one in which an ion beam is extracted from a plasma source. The ion species of interest is extracted, while other ion species are rejected. The extracted ion beam is then accelerated to increase the ion energy to a desired energy level. Typically, beam currents are very small, e.g. in the milliampere range, with a beam "footprint" area that is a few square centimeters. The ion beam may be steered in order to provide full surface coverage, or the silicon wafer may be manipulated, or a combination of beam steering and wafer manipulation may be utilized. Often, thin "screen oxides" are grown to avoid damage to the surface of the silicon wafer. Temperature control is conventionally achieved by means of backside cooling through a wafer chuck, since the wafer is kept in high vacuum.
As an ion of the ion beam enters the surface of the silicon wafer, it loses energy as the ion collides with atomic nuclei and interacts with electrons in the wafer. Each collision and electronic interaction reduces the energy of the ion until it comes to rest within the wafer. Interactions follow a statistical process, and the profile of implanted ions often approximates a Gaussian distribution. The spread of the distribution of implanted ions is characterized by standard deviation and is called the straggle.
Ion beam implantation carries a number of advantages over other methods of forming SOI structures, e.g. wafer bonding. However, the serial processing by steering an ion beam across the wafer surface limits manufacturing throughput. Furthermore, complicated ion optics are required. Complications are increased if wafer manipulation is involved. Yet another concern is that in the employment of ion beam implantation, cost efficiency often imposes a lower energy limit for ion energies, so that there is a limit of how close the peak of the Gaussian distribution of settled ions can be to the top surface of the wafer.
What is needed is a method and apparatus for increasing manufacturing throughput for the fabrication of silicon-on-insulator structures. Also needed is a method and apparatus for reducing the limit to which shallow insulator layers can be formed into a silicon-on-insulator structure.